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Proceedings of the 2006 international symposium on Low power electronics and design
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Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
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Reducing variability in chip-multiprocessors with adaptive body biasing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
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Chip-multiprocessors (CMPs) have emerged as a popular means of exploiting growing transistor budgets. However, the same technology scaling that increases the number of transistors on a single die also creates greater variability in their key power- and performance-determining characteristics. As the number of cores and amount of memory per die increase, individual core and cache tiles will become small enough that traditional sources of intra-die power and performance variations will result in tile-to-tile (T2T) variations. We start from low-level models of the phenomena involved and create models for how systematic within-die process variations, random within-die process variations, and thermal variations manifest themselves as T2T variations. Current commercial CMP designs are partitioned into fine-grained frequency islands (FIs) to allow per-core control of clock frequencies. We use our models to evaluate leveraging this partitioning to address T2T variations. Exploiting the FI partitioning improves performance by an average of 8.4% relative to the fully-synchronous baseline when both process and thermal variability are addressed simultaneously, highlighting the importance of an integrated approach. The FI design can also achieve performance 7.1% higher than the baseline at fixed power or draw 24.2% less power at equal performance.