Mitigating the impact of variability on chip-multiprocessor power and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enabling system-level modeling of variation-induced faults in networks-on-chips
Proceedings of the 48th Design Automation Conference
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
| Hi-index | 0.01 |
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for the worst case. Unfortunately, this approach has the potential to nullify much of the upcoming gains of shrinking technologies. To help understand this problem, we introduce a novel high-level and easy-to-apply model of how parameter variation affects timing errors in microprocessors. The model successfully predicts the probability of timing errors under different process and environmental conditions for both SRAM and logic units. Circuit designers can apply the model at design time to improve yield, and computer architects can use it to design processors that improve performance.