Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
A Polynomial Time Method for Optimal Software Pipelining
CONPAR '92/ VAPP V Proceedings of the Second Joint International Conference on Vector and Parallel Processing: Parallel Processing
Optimal design of synchronous circuits using software pipelining techniques
ICCD '98 Proceedings of the International Conference on Computer Design
Proceedings of the 2004 international symposium on Physical design
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositionality of Statically Scheduled IP
Electronic Notes in Theoretical Computer Science (ENTCS)
Abstraction of Clocks in Synchronous Data-Flow Systems
APLAS '08 Proceedings of the 6th Asian Symposium on Programming Languages and Systems
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell
Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus
Journal of Electronic Testing: Theory and Applications
Static scheduling of latency insensitive designs with Lucy-n
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A Scheduling Strategy for Synchronous Elastic Designs
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
MPC'12 Proceedings of the 11th international conference on Mathematics of Program Construction
Periodic scheduling of marked graphs using balanced binary words
Theoretical Computer Science
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Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: relay-stations (RS) and shell-wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can be then formally verified. As turns out, resulting behavior is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization, adding integer latencies wherever possible; residual cases require introduction of fractional registers (FRs) at specific locations. Benchmark results are presented, run on our KPASSA tool implementation.