A Scheduling Strategy for Synchronous Elastic Designs

  • Authors:
  • Josep Carmona;Jorge Júlvez;Jordi Cortadella;Michael Kishinevsky

  • Affiliations:
  • (Correspd.) Universitat Politècnica de Catalunya, Barcelona, Spain. jcarmona@lsi.upc.edu;Universidad de Zaragoza, Zaragoza, Spain. julvez@unizar.es;Universitat Politècnica de Catalunya, Barcelona, Spain. jordi.cortadella@upc.edu;Intel Corporation, Hillsboro, USA. michael.kishinevsky@intel.com

  • Venue:
  • Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
  • Year:
  • 2011

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Abstract

With the scaling of process technologies, communication delays represent a bottleneck for the performance of circuits. One of the main issues that has to be handled is the variability of such delays. Latency-insensitive circuits offer a form of elasticity that tolerates variations in those delays. This flexibility usually requires the addition of a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.