Theory of linear and integer programming
Theory of linear and integer programming
Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to Algorithms
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Structural techniques and performance bounds of stochastic Petri net models
Advances in Petri Nets 1992, The DEMON Project
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
Scheduling Synchronous Elastic Designs
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the scaling of process technologies, communication delays represent a bottleneck for the performance of circuits. One of the main issues that has to be handled is the variability of such delays. Latency-insensitive circuits offer a form of elasticity that tolerates variations in those delays. This flexibility usually requires the addition of a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.