The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
XEVE, an ESTEREL Verification Environment
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Structural Transformations Giving B-Equivalent PT-Nets
Selected Papers from the 3rd European Workshop on Applications and Theory of Petri Nets
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Optimal design of synchronous circuits using software pipelining techniques
ICCD '98 Proceedings of the International Conference on Computer Design
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Concurrency in Synchronous Systems
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
Journal of Computer and System Sciences
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell
Electronic Notes in Theoretical Computer Science (ENTCS)
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
| Hi-index | 0.01 |
We revisit the formal modeling of relay stations, which are specific connection elements used in the theory of Latency-Insensitive Design of Globally-Asynchronous/Locally-Synchronous systems. Relay stations are in charge of taking into account the physical mandatory latencies, while handling the regulation of signal/data traffic so as to avoid starvation, deadlock and congestion of local IP synchronous computation blocks. Since proposed by Carloni et al, the structure and behaviors of these relay stations have been amply characterized and analyzed. But previous works did not provide a fully formal and cycle-accurate description of these mechanisms, amenable to formal verification for instance (instead, mainly simulation models were developed). Due to the needed precision of the whole scheme we feel such a formal description might be needed. We describe such an attempt here.