Performance evaluation of concurrent systems using conflict-free and persistent Petri nets
Information Processing Letters
Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Understanding retiming through maximum average-weight cycles
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
On the analysis and optimization of selftimed processor arrays
Integration, the VLSI Journal
Theoretical Computer Science - Selected papers of the International BCS-FACS Workshop on Semantics for Concurrency, Leicester, UK, July 1990
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling Parallel Computations
Journal of the ACM (JACM)
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Hardware Design and Petri Nets
Hardware Design and Petri Nets
Coping with Latency in SOC Design
IEEE Micro
First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Issues in Implementing Latency Insensitive Protocols
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Latency-insensitive design
An algebraic theory for behavioral modeling and protocol synthesis in system design
Formal Methods in System Design
Formal Refinement Checking in a System-level Design Methodology
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Journal of Computer and System Sciences
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the initial states of retimed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dataflow Architectures for GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell
Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus
Journal of Electronic Testing: Theory and Applications
Loosely time-triggered architectures for cyber-physical systems
Proceedings of the Conference on Design, Automation and Test in Europe
A unifying view of loosely time-triggered architectures
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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Back-pressure is a logical mechanism to control the flow of information on a communication channel of a latency-insensitive system (LIS) while guaranteeing that no packet is lost. Back-pressure is necessary for building open LISs and it represents an interesting design alternative also for closed LISs because it makes possible to realize highly modular implementations with more predictable features in terms of design overhead (area, power). In discussing the role of back-pressure, we revisit the logic of the necessary building blocks, and explain the impact of the system topology on the system performance.