A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
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It is becoming necessary to have finer granularity and control ofclock domains in System-on-Chip (SoC) designs for various reasons,power consumption being the primary consideration. In this work wehave developed a mechanism to support frequency islands at thesubsystem level. This paper describes a scheme for interconnectingand allowing synchronous communication between subsystems operatingin different clock domains over a common synchronous bus interface.Our scheme provides a method to dynamically adjust the operatingfrequency of the source, target and the interconnecting bus duringthe synchronous communication while leaving other subsystems attheir preferred operating frequencies. This scheme has a smalloverhead and results in significant power savings without asignificant performance impact. When the bus utilization is lessthan 60%, our scheme results in an energy savings of 32-42%.