Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Delay Model for Router Microarchitectures
IEEE Micro
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
Feedback Control of Computing Systems
Feedback Control of Computing Systems
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
Proceedings of the 45th annual Design Automation Conference
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Proceedings of the 4th International Workshop on Network on Chip Architectures
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Proceedings of the 50th Annual Design Automation Conference
PCASA: probabilistic control-adjusted selective allocation for shared caches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we employ formal feedback control theory to achieve desired communication throughput across a network-on-chip (NoC) based multicore. When the output of the system needs to follow a certain reference input over time, our controller regulates the system to obtain the desired effect on the output. In this work, targeting a multicore that executes multiple applications simultaneously, we demonstrate how to design and employ a PID (Proportional Integral Derivative) controller to obtain the desired throughput for communications by tuning the weights of the virtual channels of the routers in the NoC. We also propose a global controller architecture that implements policies to handle situations in which the network cannot provide the overlapping communications with sufficient resources or the throughputs of the communications can be enhanced (beyond their specified values) due to the availability of excess resources. Finally, we discuss how our novel control architecture works under different scenarios by presenting experimental results obtained using four embedded applications. These results show how the global controller adjusts the virtual channels weights to achieve the desired throughputs of different communications across the NoC, and as a result, the system output successfully tracks the specified input.