Energy-efficient multicore chip design through cross-layer approach

Authors:
Paul Wettin;Jacob Murray;Partha Pande;Behrooz Shirazi;Amlan Ganguly
Affiliations:
Washington State University, Pullman;Washington State University, Pullman;Washington State University, Pullman;Washington State University, Pullman;Rochester Institute of Technology, Rochester
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty.