Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic power management of complex systems using generalized stochastic Petri nets
Proceedings of the 37th Annual Design Automation Conference
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design Challenges of Technology Scaling
IEEE Micro
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Power-Constrained Microprocessor Design
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Proceedings of the 2004 international symposium on Low power electronics and design
IEEE Spectrum
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
iTEM: a temperature-dependent electromigration reliability diagnosis tool
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TABS: temperature-aware layout-driven behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper will provide a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale---in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale---circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3-D ICs and highlights the advantages of employing hybrid Carbon Nanotube-Cu interconnects in both 2-D and 3-D designs.