ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Integrated execution: a programming model for accelerators
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power dissipation and power density have become first-order design constraints, even forhigh-performance systems. For future designs it will be the dominant constraint. In this paper we suggest a systematic approach to optimizing a processor design under (only) a power constraint. The approach uses the energy-performance ratio (EPR) of the various design parameters as the key to identifying opportunities for improving energy-efficiency.