IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2001 international symposium on Physical design
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On-chip thermal gradient analysis and temperature flattening for SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multiscale thermal analysis for nanometer-scale integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured to the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data.Both physics and implementation for the thermal simulation will be described. The code is applied to the analysis of a realistic design of CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of simulation results will be presented.