On-chip thermal gradient analysis and temperature flattening for SoC design

Authors:
Takashi Sato;Junji Ichimiya;Nobuto Ono;Kotaro Hachiya;Masanori Hashimoto
Affiliations:
Renesas Technology;Ricoh;Jedat Innovation;NEC Electronics;Osaka Univ.
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic, power density, and floorplan on thermal gradient and clock skew are studied. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.