High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
On-chip thermal gradient analysis and temperature flattening for SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast thermal simulation for architecture level dynamic thermal management
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low Power Design Essentials
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
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With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.