Efficient distributed on-chip decoupling capacitors for nanoscale ICs

Authors:
Mikhail Popovich;Eby G. Friedman;Radu M. Secareanu;Olin L. Hartin
Affiliations:
QCT, Qualcomm Corporation, San Diego, CA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY;Microwave and Mixed Signal Technologies Laboratory, Freescale Semiconductor, Tempe, AZ;Microwave and Mixed Signal Technologies Laboratory, Freescale Semiconductor, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 6
Cited 0

Scaling trends of on-chip power distribution noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Maximum effective distance of on-chip decoupling capacitors in power distribution grids

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Decoupling capacitors for multi-voltage power distribution systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Networks with On-Chip Decoupling Capacitors

Power Distribution Networks with On-Chip Decoupling Capacitors
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.