Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Scaling trends of on-chip Power distribution noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power distribution design in high-performance chips is a task that is not eased through the application of power reduction techniques. Although the average power of a high-performance design can be reduced, the peak to average power current ratio of blocks increases as a result, aggravating the challenges faced prior to average power reduction. This paper discusses the power distribution design challenge: to reliably deliver a predictable voltage to all transistors under all operating conditions. Steps in power estimation, approaches to power distribution implementation, and verification of power distribution are reviewed. The myths versus reality of power distribution design in high-performance chips are provided.