Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Conforming block inversion for low power memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Optimization of Power Grids
IEEE Design & Test
A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
An area-saving decoder structure for ROMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power charge-recycling ROM architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 µm 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM.