Cache designs with partial address matching
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 1-V 1-Mb SRAM for portable equipment
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Customization of a CISC Processor Core for Low-Power Applications
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline toggling and ultimately contributes to power reduction of the memory.