Simultaneous switching noise reduction by resonant clock distribution networks

Authors:
Behzad Mesgarzadeh
Affiliations:
-
Venue:
Integration, the VLSI Journal
Year:
2014

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Abstract

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.