Guaranteed stability with subspace methods
Systems & Control Letters
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
Modeling of Substrate Noise Injected by Digital Libraries
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Substrate model extraction using finite differences and parallel multigrid
Integration, the VLSI Journal
SWAN: high-level simulation methodology for digital substrate noise generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..