Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The impact of SOI MOSFETs on low power digital circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
SOI CMOS as a mainstream low power technology: a critical assessment
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
CMOS VLSI engineering: silicon-on-insulator (SOI)
CMOS VLSI engineering: silicon-on-insulator (SOI)
SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Converting a 64b PowerPC processor from CMOS bulk to SOI technology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SOI circuit design concepts
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
Proceedings of the 38th annual Design Automation Conference
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method.