SOI CMOS as a mainstream low power technology: a critical assessment
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
CMOS VLSI engineering: silicon-on-insulator (SOI)
CMOS VLSI engineering: silicon-on-insulator (SOI)
SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Converting a 64b PowerPC processor from CMOS bulk to SOI technology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SOI circuit design concepts
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is Silicon on Insulator (SOI). SOI devices exhibit an effect known as Parasitic Bipolar Effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid the PBE, such as transistor reordering, altering the way transistors are organized into gates, and adding pmos discharge transistors. We minimize the total cost of implementation, which includes the discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors needed by 44.23%, and reduces the size of the final solution by 11.66% on average.