A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Authors:
Basab Datta;Wayne Burleson
Affiliations:
University of Massachusetts-Amherst, Amherst, MA, USA;University of Massachusetts-Amherst, Amherst, MA, USA
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

Citing 7
Cited 0

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Parameter variations and impact on circuits and microarchitecture

Proceedings of the 40th annual Design Automation Conference
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems

IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nanometer device scaling in subthreshold circuits

Proceedings of the 44th annual Design Automation Conference
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

VLSID '08 Proceedings of the 21st International Conference on VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Process optimization and yield enhancement techniques rely on physical sensors to provide them with feedback to perform accurate process-characterization across the die. The increased susceptibility of circuit performance characteristics to parameter variations in deep sub-micron technologies motivates the need for low-overhead (area/power) and high-sensitivity process monitoring circuits which can be used by compensation schemes to tune the process and meet frequency targets or power-budgets. To this end, we have proposed and implemented in 45nm CMOS-SOI, a novel, digital, on-chip process sensing circuit with a high sensitivity of 7.1V per volt variation in NMOS Vth, low power dissipation of 13.4¼W and a compact layout occupying 45.6¼2. The design is robust towards temperature variations and supply induced noise incurring an accuracy loss of 5mV (worst-case) and 4mV (1-Ã) respectively of the NMOS threshold-voltage.