Reducing variability in chip-multiprocessors with adaptive body biasing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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The need for efficient and accurate detection schemes to mitigate the impact of process variations on the parametric yield of integrated circuits has increased in the nm design era. In this paper, a new variation detection technique is presented that uses slew as a metric along with delay to determine the mismatch between the drive strengths of NMOS and PMOS devices. The importance of considering both of these metrics is illustrated and a new slew-rate monitoring circuit is presented for measuring slew of a signal from the critical path of a circuit. Design considerations, simulation results and characteristics of the slew-rate monitor circuitry in a 45 nm SOI technology are presented, and a sensitivity of 1MHz/ps is achieved. This scheme can detect the threshold voltage variation in the order of mV, with a sensitivity of 0.95MHz/mV.