Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Robust level converter design for sub-threshold logic
Proceedings of the 2006 international symposium on Low power electronics and design
A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Investigating Crosstalk in Sub-Threshold Circuits
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
Impact of Technology Scaling on Digital Subthreshold Circuits
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
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Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.