Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Mobile applications with battery lifetimes on the order of thousands of days have placed stringent energy requirements on circuits. In this paper, we propose a new energy optimization technique for ultra-low energy circuits operating in the subthreshold regime. Our technique uses simultaneous gate sizing and supply voltage scaling to reduce energy. We demonstrate the effectiveness of our technique on benchmark circuits and offer insight on the roles of the timing distribution and wire capacitance in determining the achievable energy reductions.