A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-μm to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8x8-bit RCA multiplier. When reaching the smallest nodes, limitations come from slow scaling of the static energy consumption and the deteriorating static noise margin, which raises robustness issues when considering process variability. These effects result in a loss of energy efficiency. The use of non-minimum channel length is proposed to improve energy efficiency. At 32-nm node, it reduces total energy consumption by a factor 5.