Monte Carlo analysis of semiconductor devices: the DAMOCLES program
IBM Journal of Research and Development
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
Double-gate SOI devices for low-power and high-performance applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Leakage power for extremely scaled (Leff = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design trade-offs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart.