On-chip process variations compensation using an analog adaptive body bias (A-ABB)

Authors:
Hassan Mostafa;Mohab Anis;Mohamed Elmasry
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electronics Engineering, American University in Cairo, Cairo, Egypt;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 10
Cited 0

Parameter variations and impact on circuits and microarchitecture

Proceedings of the 40th annual Design Automation Conference
Design and reliability challenges in nanometer technologies

Proceedings of the 41st annual Design Automation Conference
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Journal of Electronic Testing: Theory and Applications
Post silicon power/performance optimization in the presence of process variations using individual well-adaptive body biasing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are demonstrated. This study shows that the proposed A-ABB reduces the standard deviations of the frequency, the dynamic power and the leakage power by factors of 6.6×, 8.8× and 3.3× respectively, when both D2D and WID variations are considered. In addition, in this presented case study, initial total yields of 16.8% and 5.2% are improved to 99.9% and 84.1%, respectively. The advantage of the proposed A-ABB is its lower area overhead allowing it to be used at lower granularity level than that of the previously published ABB circuits.