ACM SIGDA Newsletter
Design dependent process monitoring for back-end manufacturing cost reduction
Proceedings of the International Conference on Computer-Aided Design
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
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Lithographic wavelength of 193nm has been used for past few generations of patterning and is likely to remain in use for next few technology generations (at least till 28nm technology half-node) as well. This deep sub-wavelength patterning has resulted in wafer shapes not resembling drawn rectilinear shapes. The resulting non-rectangular devices and wires are not handled by current generation modeling and analyses methods. In this paper, we present a survey of electrical modeling methods for such lithographic imperfections especially on transistor layers. We also discuss use contexts of such models as well as briefly present electrical implications of the likely future patterning candidate, namely double patterning.