Design dependent process monitoring for back-end manufacturing cost reduction

Authors:
Tuck-Boon Chan;Aashish Pant;Lerong Cheng;Puneet Gupta
Affiliations:
University of California, Los Angeles;University of California, Los Angeles;Sandisk Inc.;University of California, Los Angeles
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2010

Citing 8
Cited 1

Delay Defect Screening using Process Monitor Structures

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Parametric yield estimation considering leakage variability

Proceedings of the 41st annual Design Automation Conference
Synthesizing a representative critical path for post-silicon delay prediction

Proceedings of the 2009 international symposium on Physical design
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability

Proceedings of the 46th Annual Design Automation Conference
Virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits

Proceedings of the 2009 International Conference on Computer-Aided Design
Electrical Modeling of Lithographic Imperfections

VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Analyzing the impact of process variations on parametric measurements: novel models and applications

Proceedings of the Conference on Design, Automation and Test in Europe
First-Order Incremental Block-Based Statistical Timing Analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Short-loop process monitoring structures (usually simple device I -V, C - V measurements made after M1 fabrication) are commonly put in wafer scribe-lines. These test structures are almost always design independent and measured/monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy which can accurately predict design performance based on simple Ieff-based delay and Ioff-based leakage power estimates. We show that our strategy works much better (0.99 correlation vs. 0.87) compared to conventional design-independent monitors. Further, we use the predicted delay and leakage power for early yield estimation for pruning bad wafers to save test and back-end manufacturing costs We show that wafer pruning based on our approach can achieve upto 98% of the maximum achievable benefit/profit. We design the measurement and prediction schemes so as to minimize data as well as computation that needs to be kept track of during wafer fabrication. Such design-dependent process monitoring can help target process control/optimization effort, enable quicker yield ramp besides saving test and manufacturing costs.