Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
Design challenges at 65nm and beyond
Proceedings of the conference on Design, automation and test in Europe
Can EDA combat the rise of electronic counterfeiting?
Proceedings of the 49th Annual Design Automation Conference
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
Tracking on-chip age using distributed, embedded sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 × 7.97 µm2; the post-layout power consumption is 18.57 µW during NBTI/HCI stress mode and 30.86 µW during NBTI/HCI measurement mode on average.