Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling
Proceedings of the conference on Design, automation and test in Europe
Fundamentals of Modern VLSI Devices
Fundamentals of Modern VLSI Devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different P/N ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the β-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits--from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-µm technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed P/N ratios.