Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock delayed sleep mode domino logic for wide dynamic OR gate
Proceedings of the 2003 international symposium on Low power electronics and design
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high speed and leakage-tolerant domino logic for high fan-in gates
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Clock delayed domino logic with efficient variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Mature Methodology for Implementing Multi-Valued Logic in Silicon
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Domino logic designs for high-performance and leakage-tolerant applications
Integration, the VLSI Journal
Low power wide gates for modern power efficient processors
Integration, the VLSI Journal
| Hi-index | 0.00 |
In this paper, a new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the difference and the comparison between the leakage current of the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed techniques have suffered. Moreover, using the stacking effect, leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16nm predictive technology model (PTM) demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit.