Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power high-speed 8-bit pipelining CLA design using dual-threshold voltage domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-threshold pass-transistor logic design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
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Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18@?m CMOS process from TSMC, with 10fF capacitive loads in all output nodes, using the parameters for typical process corner at 25^oC, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.