STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs

Authors:
Aseem Gupta;Nikil D. Dutt;Fadi J. Kurdahi;Kamal S. Khouri;Magdy S. Abadir
Affiliations:
University of California, Irvine;University of California, Irvine;University of California, Irvine;Freescale Semiconductor Inc., Austin, TX;Freescale Semiconductor Inc., Austin, TX
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

Citing 0
Cited 2

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Proceedings of the 7th ACM international conference on Computing frontiers
Reducing functional unit power consumption and its variation using leakage sensors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. We implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation.