Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power scalable processing using distributed arithmetic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Power aware microarchitecture resource scaling
Proceedings of the conference on Design, automation and test in Europe
IEEE Micro
A self-checking ALU design with efficient codes
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Quadruple Time Redundancy Adders
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Power-Aware Scalable Pipelined Booth Multiplier
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Computer Architecture Techniques for Power-Efficiency
Computer Architecture Techniques for Power-Efficiency
Concurrent error detection for group look-ahead binary adders
IBM Journal of Research and Development
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Architecture, Fifth Edition: A Quantitative Approach
Computer Architecture, Fifth Edition: A Quantitative Approach
Bit-sliced datapath for energy-efficient high performance microprocessors
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Low-overhead core swapping for thermal management
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Guarded evaluation: pushing power management to logic synthesis/design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An SFS Berger check prediction ALU and its application to self-checking processor designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article presents a new family of scalable arithmetic units (ScAUs) targeting resource-constrained, embedded devices. We, first, study the performance, power, area and scalability properties of general adders. Next, suitable error-detection schemes for low-power embedded systems are discussed. As a result, our ScAUs are enhanced with a suitable error-detection scheme, resulting in a Parity-Checked ScAU (PCScAU) design. The PCScAU strikes a flexible trade-off between space and time redundancy, offering dependability similar to high-end techniques for the area and power cost of low-end approaches. An alternative design, the Precision-Scalable Arithmetic Unit (PScAU) maintains throughput with degraded precision in case of hardware failures. The PScAU is targeting dependable applications where latency rather than numerical accuracy is more important. The PScAU's downscaled mode is also interesting for runtime thermal management due to its advantageous power consumption. We implemented and synthesized the PCScAU, PScAU and a few important reference designs (double-, triple- and quadruple-modular-redundancy adders with/without input gating) in 90-nm UMC technology. Overall, the PC-ScAU ranks first in 9 out of 10 power-delay-area (PDA)-product variants. It exhibits 16% area savings and 12% performance speedup for 7% increase in total power consumption, compared to the cheapest form of conventional hardware replication with the same fault coverage. The PDA product of the PCScAU is, thus, reduced by 21%. It is interesting that, while total power slightly increases, the PCScAU static power in fact decreases by 14%. Therefore, for newer technology nodes where the static power component is significant, the PCScAU can also achieve—next to performance and area -- significant power improvements.