Quadruple Time Redundancy Adders

Authors:
Whitney J. Townsend;Jacob A. Abraham;Earl E. Swartzlander, Jr.
Affiliations:
-;-;-
Venue:
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2003

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Abstract

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% - 55% reduction in hardware complexity while incurring a reasonable delay increase.