Explicit construction of linear sized tolerant networks
Discrete Mathematics - First Japan Conference on Graph Theory and Applications
Journal of Electronic Testing: Theory and Applications
Fault tolerant networks with small degree
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Optimal fault-tolerant linear arrays
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Quadruple Time Redundancy Adders
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
Fault tolerant graphs, perfect hash functions and disjoint paths
SFCS '92 Proceedings of the 33rd Annual Symposium on Foundations of Computer Science
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Towards fault tolerant parallel prefix adders in nanoelectronic systems
Proceedings of the conference on Design, automation and test in Europe
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents a systematic method for the design of a self-healing asynchronous adder. We propose a graphbased model for the design of a fault-tolerant linear array with external inputs and outputs with a minimum number of spare resources. A K-fault-tolerant asynchronous adder design is presented based on this analysis, together with the necessary support logic for dynamic self-reconfiguration. Experimental evaluations show that our method incurs both low hardware cost and small performance overhead compared to traditional approaches to fault-tolerance.