Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Carry checking/parity prediction adders and ALUs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Technique for Modular Design of Self-Checking Carry-Select Adder
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
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Future nanoelectronics based arithmetic components will enjoy abundant hardware, yet at the same time confront severe unreliability challenges. We focus on the fault tolerance of high performance parallel prefix adders (PPA), and exploit the inherent redundancy in PPAs to develop efficient fault tolerance approaches. We show that the internal invariant inherent in the parallel prefix adders provides support for online fault detection and fault masking. Furthermore, based on the particular regular structure of PPAs, an online diagnosis scheme can be developed, thus enabling the application of reconfigurability of nanoelectronics for the highly flexible online repair approaches. In contrast to traditional fault tolerance techniques that rely solely on significant external overhead, the proposed approach opens up a new genre of efficient fault tolerance techniques for arithmetic components in the nanoelectronic environment.