On implementing addition in VLSI technology
Journal of Parallel and Distributed Computing
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Heterogeneously tagged caches for low-power embedded systems with virtual memory support
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Circuit sizing and supply-voltage selection for low-power digital circuit design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
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Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for these regions of operations. This paper demonstrates that the use of more complex highperformance structures combined with scaling of the supply-voltage outperforms traditional low-power oriented designs in the low- and ultra low-power domain.