Power-Aware Scalable Pipelined Booth Multiplier

Authors:
Hanho Lee
Affiliations:
The author is with the School of Information and Communication Engineering, Inha University, Incheon, 402-751, Republic of Korea. E-mail: hhlee@inha.ac.kr
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2005

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Abstract

An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications.