A power-aware variable-precision multiply-accumulate unit

Authors:
Jin-Kyu Chang;Hanho Lee;Chang-Seok Choi
Affiliations:
School of Information and Communication Engineering, Inha University, Incheon, Korea;School of Information and Communication Engineering, Inha University, Incheon, Korea;School of Information and Communication Engineering, Inha University, Incheon, Korea
Venue:
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
Year:
2009

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Abstract

An energy-efficient power-aware design is highly desirable for digital signal processing (DSP) functions that encounter a wide diversity of operating scenarios in batterypowered wireless sensor network systems. Addressing this issue, this paper presents a power-aware variable-precision multiply-accumulate (VP-MAC) unit that makes use of dynamic-range detection unit and a 16-bit scalable Baugh-Wooley Multiplier with fixed-width error compensation circuit for DSP applications. The proposed VP-MAC contains both an 8-bit and a 16-bit multiplier and has input gating to route the data to appropriate hardware. When 16-bit multiplication is needed, the entire multiplier is used. However, if only 8-bit multiplication is needed, the 8-bit logic is enabled. Simulated and measured results show a reduced power-consumption of 43% and reduced gate count of 42.7% respectively, in comparison with conventional power-aware scalable pipelined MAC unit.