Organization of Large Scale Fourier Processors
Journal of the ACM (JACM)
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A power-aware variable-precision multiply-accumulate unit
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
A power-driven multiplication instruction-set design method for ASIPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable power-aware scalable booth multiplier
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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Energy-aware design is highly desirable for systems that encounter a wide diversity of operating scenarios. This is in contrast to traditional low power design for the worst case scenario, which may not be globally energy efficient. Energy-aware design focuses on enabling architectures which scale down energy as quality requirements are relaxed. A new energy-scalable system design methodology is proposed for a Real-Valued FFT processor which supports variable bit precision (8 and 16-bit precision) and variable FFT length (128- 512 point). Two energy-aware architectures, Ensemble of Point Solutions method and Reuse of Point Solutions method, are described and evaluated. Simulated and measured results show a 66% energy savings for 8-bit datapath and 52% savings for 128-point FFT length over a non-scalable approach.