MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs
SIAM Journal on Scientific Computing
A system-level energy minimization approach using datapath width optimization
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Data memory design considering effective bitwidth for low-energy embedded systems
Proceedings of the 15th international symposium on System Synthesis
Variable size analysis and validation of computation quality
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Energy-aware architectures for a real-valued FFT implementation
Proceedings of the 2003 international symposium on Low power electronics and design
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
| Hi-index | 0.00 |
This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.