A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
A Digit-Serial Structure for Reconfigurable Multipliers
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Truncated Online Arithmetic with Applications to Communication Systems
IEEE Transactions on Computers
Minimum Mean Running Time Function Generation Using Read-Only Memory
IEEE Transactions on Computers
Arithmetic for Ultra-High-Speed Tomography
IEEE Transactions on Computers
A Two's Complement Array Multiplier Using True Values of the Operands
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
Synthesis and Comparison of Two's Complement Parallel Multipliers
IEEE Transactions on Computers
Multi-functional floating-point MAF designs with dot product support
Microelectronics Journal
Negative Save Sign Extension for Multi-term Adders and Multipliers
Journal of Signal Processing Systems
Fixed-width multipliers for the implementation of efficient digital FIR filters
Microelectronics Journal
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
International Journal of Reconfigurable Computing
Partitioning and gating technique for low-power multiplication in video processing applications
Microelectronics Journal
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers
Journal of Signal Processing Systems
Microelectronic architectures and devices for signal and symbol processing
Integration, the VLSI Journal
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel, low-power array multiplier architecture
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
A power-aware variable-precision multiply-accumulate unit
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
Proposal for an efficient reconfigurable fixed-width multiplier
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Truncated binary multipliers with variable correction and minimum mean square error
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Cascading Transmission Gates to Enhance Multiplier Performance
IEEE Transactions on Computers
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology
Microelectronics Journal
Review: New redundant logic design concept for high noise and low voltage scenarios
Microelectronics Journal
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
Analog Integrated Circuits and Signal Processing
A Signed Array Multiplier with Bypassing Logic
Journal of Signal Processing Systems
Reconfigurable multiple operation array
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Dynamic voltage scaling for power aware fast fourier transform (FFT) processor
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Reduced redundant arithmetic applied on low power multiply-accumulate units
EHAC'12/ISPRA/NANOTECHNOLOGY'12 Proceedings of the 11th WSEAS international conference on Electronics, Hardware, Wireless and Optical Communications, and proceedings of the 11th WSEAS international conference on Signal Processing, Robotics and Automation, and proceedings of the 4th WSEAS international conference on Nanotechnology
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
On carry-save strategies for multiply-accumulate arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
Low power energy efficient pipelined multiply-accumulate architecture
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Faster and energy-efficient signed multipliers
VLSI Design
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An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.