Carry-save architectures for high-speed digital signal processing
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Digital Processing of Signals: Theory and Practice
Digital Processing of Signals: Theory and Practice
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Reviewing 4-to-2 Adders for Multi-Operand Addition
Journal of VLSI Signal Processing Systems
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
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Carry-save arithmetic is frequently used in multiplier design. When reducing an array of partial products by carry-save addition, one cannot be certain, which carry-save strategy yields the best results in terms of area, latency, and low power consumption. In our contribution, we expose differences between the strategies of Wallace and Dadda, as well as our carry-save reduction method called short result reduction strategy--SRR, when applied to various arithmetic operations. We provide a software tool for time efficient analysis and rapid prototyping of carry-save arithmetic using strategies of this kind. We show results gained by employing our tool in terms of the expected area, latency, and power consumption of the resulting circuit, and outline the relevance for low power design.