Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Reduced redundant arithmetic applied on low power multiply-accumulate units
EHAC'12/ISPRA/NANOTECHNOLOGY'12 Proceedings of the 11th WSEAS international conference on Electronics, Hardware, Wireless and Optical Communications, and proceedings of the 11th WSEAS international conference on Signal Processing, Robotics and Automation, and proceedings of the 4th WSEAS international conference on Nanotechnology
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
On carry-save strategies for multiply-accumulate arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
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The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from 驴1 to one least significant bit below +1. Either the multiplication of 驴1 驴 驴1 or taking the absolute value of 驴1 produces a result (+1) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above 驴1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.