Carry-save architectures for high-speed digital signal processing
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
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We propose a new redundant approach on designing multiply-accumulate units for low power. State of the art implementations make use of redundant registers to obtain low delay times by moving any carry propagate adder out of the operation cycle. Our contribution is optimizing the level of redundancy by adjusting the size of the carry register. This optimization is performed by a VHDL generator, creating a carry save reduction tree meeting given delay constraints. This generator uses a delay-driven, list-based algorithm, optimized by synthesis timing results. With this method, the carry register and final carry propagate adder are shortened. Applying our reduced redundant approach to different sized twos complement multiply accumulate units under low power constraints, we gain delay savings up to 21 percent without increased area or power for 16 bit multiply-accumulate units and up to 6 percent for 32 bit multiply-accumulate units.