Carry-save architectures for high-speed digital signal processing
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
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It is well known that multipliers using Dadda trees need less area and still can be faster than Wallace trees when considering different latencies on the paths through the counters used for reduction. In our contribution we show that for multiply-accumulate units, a hybrid strategy based on both Wallace and Dadda reduction can easily outperform pure Dadda trees.